Sessions Index

S19 【S19】Deep Learning for Geometry & Mechanics Prediction

Oct. 22, 2025 13:00 PM - 15:00 PM

Room: 504 c, TaiNEX 1
Session chair: Shu-Shen Yeh/Google, Cadmus Yuan/Feng Chia University

AI-Enabling the Solder Height Prediction
發表編號:S19-1時間:13:00 - 13:15

Paper ID:AS0008
Speaker: Law Yi Kei Owen
Author List: Yi Kei Owen Law, Haibo Fan, Caroline Beelen-Hendrikx, Nick Chenchao Zhong, Anson Song

Bio:
Owen Law is a Principal Engineer from Package R&D – Package Design and Modeling, Nexperia Hong Kong. He got his PhD degree from Hong Kong University of Science and Technology. Before he join Nexperia HK, he worked in ASM Hong Kong around 14 years. He focused on semiconductor machine design, manufacturing, and reliability testing. Owen has two granted IPs and is Charted Engineer in IET.


Abstract:
The design of power packages with both high efficiency and high-power density performance while maintaining the highest possible reliability is a challenge. Cu-pillar bumping is a next-generation flip chip interconnection between chip & packages (FCBGA/FCCSP), especially for fine pitch applications. Therefore, one of concerns is the relationship between the initial solder height, pillar shape and solder height after reflowing processes . Especially when mixing bump shapes are used in a die without resulting in too large differences in height after reflowing. To reduce the workload of designers to do technical simulation and working time, artificial neural network prediction and third order polynomial surface fitting are used to predict the reflowed solder height and inter-comparison. Both can be obtained <5% error by comparison with surface evolver simulation results.


 
Effect of Process Parameters and Their Interactions on Packaging Process in System in Package Structure
發表編號:S19-2時間:13:15 - 13:30

Paper ID:TW0132
Speaker: Sheng-Jye Hwang
Author List: Yu-Li Chen, Li-Ting Huang, Sheng-Jye Hwang

Bio:
Professor Sheng-Jye Hwang received the Ph.D. degree in mechanical engineering from the University of Illinois at Urbana–Champaign, Champaign, IL, USA, in 1992. He has been a Faculty Member with National Cheng Kung University, Tainan, Taiwan, since 1992, where he is currently a professor. He has more than 96 SCI journal articles published in the areas of polymer processing, electronic packaging, 3D printing and computer-aided engineering. He is actively involved in industry-academic cooperating researches and has several technology transfers to the industry.


Abstract:
With the advancement of IC advanced packaging technology, improving the process yield and reliability of packaging products has become a significant challenge. For manufacturers, experimental testing and verification require considerable time, financial investment, and production equipment utilization. In recent years, to reduce R&D and testing costs, simulation-based process prediction and analysis have become a key investment focus. Therefore, this study utilizes Moldex3D molding simulation software to analyze System in Packaging (SiP) and establish an optimization process based on Taguchi methods while investigating the importance of interaction effects on process parameters.
To optimize the process, various models are employed to describe the flow and deformation behavior of the package. During the simulation, the Cross-Castro-Macosko viscosity model and Kamal’s cure kinetics model are used to simulate the effects of temperature and degree of cure on the flow behavior of EMC. Meanwhile, Post-Mold Curing (PMC) solver is adopted for warpage prediction, integrating the two-domain modified Tait P-V-T-C model and the dual shift factor model to account for curing shrinkage, CTE mismatch, and viscoelastic behavior. This approach enables more accurate simulation and prediction. The initial parameter analysis identifies that air traps issues predominantly occur behind large chips, attributed to the uniform flow front reaching multiple components simultaneously, leading to air traps phenomena. Furthermore, the study accurately predicts warpage and von Mises stress distribution, which serves as the basis for subsequent multi-objective optimization.
The multi-objective optimization is conducted in two stages: without considering interaction effects and considering interaction effects. In the first stage, key quality indicators including air traps quantity, after PMC warpage, and after PMC average von Mises stress, are optimized using Taguchi methods to evaluate the influence of different process parameters on quality characteristics. A low-resolution orthogonal array (three-level resolution) is initially used for optimization analysis, revealing that the optimal parameter sets for different quality characteristics vary. In the air traps analysis, the most influential factor is the component placement angle; in the warpage analysis, the most significant factor is the ratio of solder mask to prepreg; and in the von Mises stress analysis, the most critical factor is the mold temperature, indicating conflicts and trade-offs among them. However, since low-resolution orthogonal arrays may lead to confounding effects between main effects and interaction effects, the study further considers interaction effects using a high-resolution orthogonal array (five-level resolution) for in-depth analysis.
Results indicate that when interaction effects are considered, the optimized parameter sets differ from the initial analysis and successfully reduce all quality indicator values. The verification simulations confirm that the optimized parameters meet expectations. Additionally, the analysis reveals that PMC duration alone does not significantly affect quality characteristics but exhibits strong interaction effects with Solder Mask and Prepreg ratio, and mold temperature. This finding emphasizes that both main effects and interaction effects jointly influence quality characteristics, highlighting the critical role of considering interaction effects in determining optimized process parameters.


 
Pattern Shapes Prediction in Cross-sectional Images and Proposing Processes with Neural Network
發表編號:S19-3時間:13:30 - 13:45

Paper ID:AS0033
Speaker: Kohei Motojima
Author List: Kohei Motojima, Hayato Sugiyama, Kaede Ameyama, Chiho Ueta

Bio:
Kohei Motojima earned his Master's degree in Materials Informatics from Meiji University in Japan, graduating in 2023. Since joining Taiyo Holdings Co., Ltd. in the same year, he has been focused on research involving AI and simulation technologies for packaging materials.


Abstract:
Recently, with the development of AI and Big Data, semiconductor packages are required to have high computation capability. To achieve this, semiconductors are miniaturized, and semiconductor packages are becoming denser and larger. Therefore, controlling the pattern shapes of package materials is essential because they affect long-term reliability. To control pattern shapes, it is necessary to polish and observe cross-sections. The time cost of polishing and observation is over 70% in the observation process of package materials. Additionally, polishing depends on the operator's skill. Hence, to speed up process establishment, it's desirable to reduce the number of experiments and polishing.
In the field of semiconductor resist, there is pattern shape simulation. Using this, we can reduce the number of experiments because we can calculate pattern shapes before conducting them. However, in the field of package materials, there is no simulation of pattern shape. Package materials don’t have the theory of pattern shape to construct simulations because they are complex materials.
In this study. We tried to construct a novel system that reduces destructive cross-sectional observation. To achieve this objective, we used machine learning. Machine learning doesn't require a theory because AI learns the relationship between input data and output data. Novel system combines regression analysis (RA) and variational autoencoder (VAE) which is a type of deep neural network that specializes in image generation. VAE consists of two models: encoder and decoder. The encoder reduces high-dimensional input data to lower-dimensional latent variables Z. By inputting Z into the decoder, the original high-dimensional data is reconstructed. We constructed a VAE model trained with cross-sectional images and RA models that predict Z from experimental conditions. By inputting the predicted Z into the decoder, we can predict pattern shape in cross-sectional images.
As a case study, we dealt with solder resist (SR) cross-sectional images. SR is a negative photosensitive material and has many required functional properties among packaging materials. Generally, it takes several days to several weeks to observe cross-sections from substrate fabrications. The theory of pattern shape has not yet been established.
We constructed the VAE model and RA models. Experimental conditions were spectra and other conditions. Spectra consists of SR absorbance, PET absorbance, substrate reflectance, and exposure intensity. Other conditions consist of dose, development temperature, water temperature, etc. We successfully predict cross-sectional images from experimental conditions.
Next, we tried to optimize process conditions. By inputting the cross-sectional image that we wanted into our system. Our system searched and proposed some process conditions to achieve the inputting cross-sectional image. We experimented under proposal experimental conditions. We got the wanted pattern shape in only a few days.
We succeeded in constructing a novel system to predict pattern shape. It takes only a few seconds from inputting process conditions to outputting cross-section images. The system can reduce destructive cross-sectional observation, which is a significant experimental cost in processing process establishment for packaging materials.


 
Hybrid Machine Learning-Based Warpage Prediction for Fan-Out Panel Level Packaging
發表編號:S19-4時間:13:45 - 14:00

Paper ID:TW0178
Speaker: Ya-Chi Chen
Author List: Ming-Ching Huang, Ya-Chi Chen and Kuo-Ning Chiang

Bio:
The speaker is currently a graduate student at National Tsing Hua University, specializing in the simulation of warpage behavior in Fan-Out Panel Level Packaging (FO-PLP). Her research combines nonlinear viscoelastic–plastic modeling and finite element analysis with machine learning techniques to efficiently predict thermomechanical deformation and improve packaging reliability.


Abstract:
As Moore’s Law approaches its limit, Fan-Out Panel Level Packaging (FO-PLP) has emerged as a promising solution, offering high I/O density and excellent area efficiency. However, during the FO-PLP process, the package undergoes multiple stages involving repeated heating and cooling cycles, which often lead to severe warpage. This deformation is primarily caused by two factors. First, the mismatch in coefficients of thermal expansion (CTE) between different materials generates internal stresses due to mutual constraint. Second, cure shrinkage occurs in thermosetting polymers, particularly the Epoxy Molding Compound (EMC), as crosslinking reactions progress under thermal loading. These combined effects can significantly reduce the package’s yield and reliability.
This study employs a nonlinear rheology viscoelastic–plastic material model to simulate the nonlinear behavior of EMC, a complex thermosetting polymer, under thermal cycling. A 3D FO-PLP package model (320 mm × 320 mm) is established using the Finite Element Method (FEM), which reflects actual processing conditions to capture the warpage profile after debonding.
While FEM provides accurate simulation results, its high computational cost makes it impractical to simulate each design condition individually. To overcome this, a hybrid machine learning framework is developed to efficiently predict warpage based on FEM-generated data. The framework integrates three key techniques in sequence: Random Forest (RF), K-means clustering, and Artificial Neural Networks (ANN). RF is first used to classify the warpage pattern based on design parameters and estimate the probability of each pattern. This step captures the complex relationships between geometric inputs and resulting warpage behaviors, and also provides probability estimates used to weight the outputs of pattern-specific prediction models.
Next, Cluster Analysis is applied to reduce the size of the dataset by selecting representative points. This step reduces training time while retaining essential differences in geometric parameters. Finally, two separate ANNs are constructed for different warpage shape categories. These models are trained independently on design parameters to capture detailed deformation behavior. Their outputs are aggregated using Ensemble Learning, with RF-estimated probabilities serving as weighting factors. This structure enables the model to use its classification probability to guide accurate prediction of each warpage pattern.
The proposed framework not only improves prediction precision but also significantly reduces the computational cost of traditional FEM analysis, enabling more efficient warpage evaluation across varying FO-PLP designs.


 
Improving Substrate Warpage Control in Flip Chip Bonding via Optimized Cover Jig Design with Reinforcement Learning
發表編號:S19-5時間:14:00 - 14:15

Paper ID:TW0235
Speaker: Chi-Hua Yu
Author List: Chi-Hua Yu , Guan-You Chen , Wei-Long Chen , Ming-Han Chong

Bio:
Professor Chi-Hua Yu is a scholar in artificial intelligence and advanced semiconductor packaging, with expertise in multiscale modeling and computational mechanics. He earned his Ph.D. from National Taiwan University in 2014 and conducted postdoctoral research at the Massachusetts Institute of Technology (MIT) from 2018 to 2020. Since 2020, he has been a faculty member at National Cheng Kung University, where his research focuses on applying AI techniques—such as deep learning, reinforcement learning, and generative modeling—to the design and optimization of electronic packaging systems. His work addresses key challenges in thermal management, mechanical reliability, and structural innovation for 2.5D/3D IC and fan-out packaging technologies. In parallel with his academic role, Prof. Yu is the founder and Chief Technology Officer of NeuroShine Ltd. Co., a university spin-off committed to developing AI-driven EDA tools for intelligent semiconductor design and advanced manufacturing. His combined academic and entrepreneurial efforts seek to bridge artificial intelligence with next-generation electronic system design.


Abstract:
Flip-Chip Bonding (FCB) has become a cornerstone technology in the advancement of electronic packaging. By flipping the chip and directly attaching it to the substrate using micro-bumps, FCB significantly shortens interconnect lengths, lowers electrical impedance and signal delay, enhances bandwidth, improves heat dissipation, and increases packaging density. These advantages make FCB indispensable in high-performance electronic systems. However, one persistent challenge lies in the mismatch of coefficients of thermal expansion (CTE) between the chip and the substrate. During high-temperature processes such as reflow, this mismatch generates thermal stress concentrations, which can result in solder joint cracking, interfacial delamination, and excessive warpage—ultimately degrading the structural integrity and reliability of the package.
To address the issue of warpage induced by CTE mismatch, this study focuses on optimizing the geometric design of a magnetic cover jig used in the FCB assembly process. The cover jig plays a critical role in applying constraint forces during reflow to control deformation. Traditional optimization methods rely heavily on domain expertise and repeated simulations across diverse material and process conditions. Such trial-and-error strategies are often time-consuming and resource-intensive, making them impractical for rapid design iteration. To overcome this bottleneck, we propose a reinforcement learning (RL)-based design framework capable of autonomously exploring high-dimensional design spaces to identify optimal geometric parameters for the cover jig.
A high-fidelity finite element model was first established using Abaqus, incorporating realistic thermal loading profiles, fixed boundary conditions, and complex multi-surface contact interactions to faithfully replicate actual manufacturing scenarios. While Abaqus provides a graphical user interface (GUI), it also supports Python scripting, which we leveraged to automate the entire simulation process. Through seamless integration of Python-based geometry generation, simulation control, and result extraction, we constructed a fully automated design-evaluation loop. This loop is connected to an RL agent that iteratively learns from simulation feedback and adjusts the design parameters to improve warpage performance.
Importantly, our approach does not aim merely to minimize absolute warpage. In real-world conditions, a perfectly flat substrate does not necessarily guarantee successful bonding. Due to thermal stress, geometric asymmetry, or material heterogeneity, the die itself may exhibit intrinsic warpage. Over-flattening the substrate may lead to misalignment during bonding, causing local stress concentrations and potential reliability issues. Therefore, achieving warpage compatibility between the substrate and die is crucial for high-precision packaging.
To this end, we propose an engineering-oriented scoring system that enables the RL model to go beyond single-objective optimization. Instead of blindly pursuing minimal warpage, the model is trained to generate specific warpage profiles that align with the deformation contour of the die. By matching the spatial warpage distribution of the substrate to that of the die, we enable more effective mechanical coupling and stress mitigation during bonding. This strategy not only enhances the quality of die-to-substrate attachment but also improves overall yield and long-term package reliability.


 
Parallel-Accelerated Neural Network-Based Lifetime Prediction and Design Optimization for Wafer-Level Packages Using Finite Element Simulation
發表編號:S19-6時間:14:15 - 14:30

Paper ID:TW0188
Speaker: Chang-Hsu Lo
Author List: Yu-Ting Su, Chang-Hsu Lo, Kuo-Ning Chiang

Bio:
The speaker is a graduate student at National Tsing Hua University, focusing on reliability simulation of wafer-level packaging. His work involves finite element analysis and AI-assisted modeling methods to accurately predict solder fatigue life under thermal cycling.


Abstract:
Wafer-Level Packaging (WLP) has become a key technology in modern semiconductor manufacturing, enabling high-density integration, excellent thermal performance, and reduced form factors. However, solder joints in WLP are highly susceptible to fatigue failures under thermal cycling, making accurate lifetime prediction of solder balls essential for reliability assessment. While finite element analysis (FEA) provides accurate predictions, it is computationally expensive and inefficient when evaluating a wide range of design variations.
To address this issue, we propose an AI-assisted framework that integrates experimentally validated simulation models with machine learning techniques for efficient solder ball fatigue life prediction during the design phase. Initially, FEA models were manually constructed and validated against experimental thermal cycling test data across five WLP configurations (TV1–TV5). Once the accuracy of manual modeling was confirmed, a Python-based automated script was developed to generate 2D ANSYS models based on design parameters. The automatically generated model under the TV2 configuration was further validated by comparing results against both manual simulation and experimental data. Upon confirming that the prediction errors were sufficiently small, we generated a large dataset with varying solder ball geometries and package structures for machine learning training.
We then trained multiple supervised learning models using the simulated dataset, including Artificial Neural Networks (ANN), Recurrent Neural Networks (RNN), Support Vector Regression (SVR), Kernel Ridge Regression (KRR), Gaussian Process Regression (GPR), Random Forest (RF), Extra Trees (ET), k-Nearest Neighbors (KNN), and Polynomial Regression (PR). To explore the impact of dataset size on model performance, we designed six different training dataset sizes (256, 625, 1296, 2401, 4096, and 9000 samples). Each model underwent grid search-based hyperparameter tuning and was tested with various data preprocessing strategies.
The results show that, with appropriate model selection and training data size, prediction errors can be maintained within 1% of FEA simulation results, while significantly reducing the simulation time required during early-stage package design. We further conducted a systematic comparison of training time and prediction accuracy for each algorithm under different data scales, aiming to identify models that provide optimal trade-offs between computational efficiency and predictive precision. This study demonstrates the feasibility and practicality of data-driven AI models for solder ball fatigue life prediction, offering a scalable approach for future extension to 3D packaging or other complex reliability scenarios.

Keywords – Wafer-Level Packaging (WLP), Finite Element Method, Solder Ball Fatigue Life Prediction, Artificial Intelligence, Machine Learning.


 
Warpage Behavior Prediction of Multi-layer RDL in Fan-out Wafer-level Packaging Based on Artificial Neural Networks
發表編號:S19-7時間:14:30 - 14:45

Paper ID:TW0139
Speaker: Sheng-Jye Hwang
Author List: Chih-Ping Hu, Chun-Chieh Hung, Sheng-Jye Hwang, Chun-Hung Sun

Bio:
Professor Sheng-Jye Hwang received the Ph.D. degree in mechanical engineering from the University of Illinois at Urbana–Champaign, Champaign, IL, USA, in 1992. He has been a Faculty Member with National Cheng Kung University, Tainan, Taiwan, since 1992, where he is currently a professor. He has more than 96 SCI journal articles published in the areas of polymer processing, electronic packaging, 3D printing and computer-aided engineering. He is actively involved in industry-academic cooperating researches and has several technology transfers to the industry.


Abstract:
With the advent of artificial intelligence, semiconductor process nodes continue to advance to meet the demands of high-performance computing (HPC) chips for high-speed computation and massive data transmission. Chip packaging technologies have also evolved to address design challenges such as high bandwidth and large counts of I/O, extending from traditional 2D packaging to advanced 2.5D and 3D architectures. Among these, Fan-out Wafer-level Packaging (FOWLP), with its high routing density, excellent electrical performance, and effective heat dissipation capabilities, has been widely adopted in high-end chips and mobile devices, becoming one of the most prominent packaging technologies in recent years.

However, the FOWLP process involves multiple cycles of high-temperature heating and cooling, during which differences in the thermal properties of materials can lead to structural warpage. If the amount of warpage exceeds the allowable range, it can reduce process yield, cause packaging failures, or hinder subsequent process integration, ultimately affecting product reliability. Therefore, accurately predicting warpage behavior at each stage of the packaging process has become a key issue for improving process stability and packaging yield.

This study focuses on the FOWLP structure and conducts thermal stress simulation analyses of various stages in the RDL-first process, investigating the influence of different process temperature settings on warpage behavior. Using finite element simulation tools, six actual structural and material combinations were systematically analyzed and validated against experimental measurement data. The results show that the simulation process established in this study maintained a maximum error of within 20% across all cases, demonstrating good accuracy and reliability. Notably, simulations using the average reference temperature setting were the most consistent with experimental values, slightly overestimating the actual warpage, enhancing the warpage prediction's accuracy and credibility.

Building on this foundation, machine learning techniques were introduced. Based on data generated from simulations, warpage prediction models were trained using algorithms such as XGBoost and artificial neural networks (ANN). Feature selection and hyperparameter optimization were applied to improve model accuracy, successfully controlling the prediction error within 15%.
Compared with traditional approaches that construct separate prediction models for each specific structure type, this study proposes a recursive input modeling mechanism based on the number of structural layers. This enables the model to accommodate varying package stack designs and supports layer-by-layer recursive prediction.

To further enhance the generalizability and practical applicability of the model, a sequential prediction strategy was adopted to build a single recursive neural network architecture. It allows the model to estimate the warpage behavior of subsequent layers based on the predicted results of previous layers. This method overcomes the limitations of training separate models for each packaging configuration, significantly reducing the need for finite element simulation data and lowering the time cost of model training while improving model scalability and adaptability for multi-layer package designs.

This study combines finite element simulation with machine learning-based recursive prediction methods to establish an accurate and highly scalable warpage prediction framework. It is expected to serve as a valuable tool for early-stage warpage evaluation and process optimization in advanced packaging design, enhancing packaging development efficiency and process stability.


 
Mechanistic Study of CMP Retainer Rings for Wafer-Edge Integrity
發表編號:S19-8時間:14:45 - 15:00

Paper ID:TW0050
Speaker: You-Sheng Song
Author List: You-Sheng Song, Cheng-Chieh Lee, Mei-Ling Wu

Bio:
You-Sheng Song is the Bachelor of Science (B.S.) in Department of Mechanical and Electro-mechanical Engineering at National Sun Yat-sen University. He is an IEEE Student Member in 2025. He has been working in the general areas of microelectronic packaging, simulation mechanics, and dynamic material response packaging since joining the member of the MOEMS laboratory group in 2024. His research involves analyzing, and modeling the failure mechanisms in Chemical Mechanical Polishing (CMP). The research is leading to practical approaches for microelectronic package design. Over the past 2 years, he has been working extensively in the area of dynamic loading of mechanical and CMP Retainer Rings for Wafer-Edge Integrity. In 2024, he has participated in an industry academia collaboration project with TSMC with Professor Mei-Ling Wu.


Abstract:
This study focuses on Chemical Mechanical Polishing (CMP), a process involving a three-body rotational system composed of a polishing pad, wafer, and retaining ring, working in conjunction with polishing slurry. Polishing pads form a stable grinding reference surface through high rigidity carrier platen, while wafer rely on independent airbags in multiple zones to clamp and rotate in synchronization with carriers or with a slight difference in speed to achieve fine and uniform material removal. Over prolonged polishing durations, retaining ring undergoes deformation, which causes uneven pressure distribution and thickness reduction at silicon wafer edge. This research employs finite element method simulation (LS-DYNA), experimental validation, and theoretical analysis to investigate mechanisms of retaining ring geometry and material properties affecting stress distribution and thickness thinning at wafer edge. Through analytical simulation strategies, we predict wear behavior and structural deformation of retaining ring under 100 hrs. of continuous polishing. By comparing simulation model with empirical data, study aims to extend lifespan of retaining ring and reduce wafer edge damage. Future results are expected to be applied to smart CMP process monitoring and fixing ring design optimization to improve wafer edge quality and production line reliability.


 


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