Sessions Index

Bio:

Dr. Chong Leong, Gan received his B.S. degree in Chemical Engineering from National University of Malaysia in 2000, M.S. degree in Chemical Instrumentation in 2003 from University Science Malaysia, and Ph.D. in Nanoelectronic Engineering from University Malaysia Perlis, Malaysia in 2015. He is Senior Member of IEEE, Fellow of Institution of Engineering and Technology, Fellow of Institute of Materials, Minerals & Mining, UK., Fellow of Institute of Physics, UK., and Royal Society of Chemistry, UK. Since 2000, he has been with Silterra Malaysia, Quality and Reliability MTS with Altera, Product Engineering with Osram Opto-Semiconductors, Broadcom, R&D Engineering with SanDisk and currently working as Package Characterization Director with Micron Taiwan. He is recipient of IEEE EPS Distinguish Technical Leadership Certificate in 2021, Emerald Outstanding Journal Reviewer in 2021 and ASME JEP Reviewer of the Year in 2022. His research interests including semiconductor packaging reliability, electronic packaging materials characterization, nanomaterials, and radiation reliability. He has published more than 75 international journal articles, 1 book with Springer Publisher. CL serves as Editorial boards with more than 25 international journals, Guest Editor with Elsevier Materials Science in Semiconductor Processing and Emerald Microelectronics Internal journals. He has 30 patents issued/ filing in US and China patent offices.

Abstract:

  With the recent innovation of Open AI (Artificial Intelligence) and AI humanoid robots’ applications, this has triggered the growth of data center infrastructure as processing, storage, and communication system in the digital world. The data center itself has contributed 1.5 % to the total world electricity consumption and this is expected to increase with time. Continuous higher demand for low power, larger data storage and faster data rates are pushing the suppliers to provide the advanced packages solutions such as NAND-Based MCP (Multiple Chip Package), HBM (High Bandwidth Memory), immersion-cooled and future cryogenic memory computing in AI
deployments in datacenters, humanoid robots as well as future quantum computing.
  This talk lays out the technical requirements of semiconductor electronics materials roadmaps, development, and properties with closer interactions on packaging robustness. It encompasses its package strength, component and solder joint reliability, package warpage performance, thermal dissipation as well as radiation induced soft errors, which become more important due to higher susceptibility of these packages to external thermal-mechanical stresses in AI datacenter applications. Evolution of these key assembly materials will be discussed in terms of its technical challenges and enabling reasoning as well as possible failure modes and mechanisms to address the needs and callouts for identifying those key materials characteristics which are critical to memory system level packaging.

 

Bio:
Satoshi Osawa is a research and development engineer at NIHON GOSEI KAKO Co., Ltd., where he is engaged in the development of epoxy resin-based encapsulant compounds for electronic and electrical applications. His work focuses on optimizing the formulation of liquid-type epoxy compounds to meet stringent reliability requirements, such as heat shock resistance. In this presentation, he introduces the features and reliability performance of an existing liquid encapsulant developed by the company, highlighting its suitability for electronic applications and its potential to streamline manufacturing processes.

Abstract:
[Introduction]
Epoxy resin encapsulants play an important role in electronic and electrical applications such as semiconductors. Epoxy resin encapsulants has good providing vibration isolation, waterproofing, chemical resistance, and component protection. However, optimal resin compounding is required to pass long term reliability tests such as the heat shock tests.
In this study, we report on the design concept of materials that can withstand heat shock tests and the characteristics of our newly developed product.

[Investigation]
-material design concepts that can withstand heat shock tests-
1) design the material so that the Tg exceeds the required heat resistance temperature, and set the Tg within the α1 range.
2) blend in a flexible resin with a Tg below the required heat resistance temperature to allow it to follow changes in other components

[Representative issues with current flexible resins]
・silicone resin: excellent heat and water resistance, but issues include contact failure due to siloxane, adhesion, and cost
・urethane resin: reasonable price, but issues with heat resistance, water resistance, and chemical resistance
・epoxy resin: excellent in strength, toughness, chemical resistance, etc., but many filler-blended products are hard and flexible products are rare. In addition, two-liquid type epoxy resins entrap air when mixed, so air bubbles on the surface and inner cured product are an issue.

-characteristics of the newly developed product ER-6506-
Er-6506, which we developed, is a two-liquid type epoxy resin-based encapsulant, but the cured product is flexible, so it can be used as an encapsulant for electronic and electrical applications that satisfy reliability evaluations such as heat shock tests. Furthermore, er-6506 has high fluidity and good bubble breaking properties, so a cured product with excellent appearance can be obtained even without a degassing process. This may contribute to simplifying production lines and reducing manufacturing costs.

 

Bio:
Dr. Thomas is a highly qualified professional, having obtained his PhD in Chemistry from the prestigious Freie Universität Berlin in Germany. Dr. Thomas joined MKS Atotech as a R&D scientist in 2014. Since 2019, Dr. Thomas has held the position of Global Product Manager in the Electronics Business division at MKS Atotech.

Abstract:
As IC substrate technology advances towards fine lines and higher circuit densities, there is an increasing demand for copper (Cu) surface preparation to ensure reliable adhesion with lamination materials and resistance to external stress conditions. At the same time, it is essential to ensure process efficiency and support signal integrity. Conventional approaches often rely on multi-step roughening techniques to maintain adhesion in the presence of thermal, humid and chemical stresses between Cu and the dielectric. However, these techniques compromise the integrity of the Cu surface and are incompatible with the requirement for ultra-smooth conductors.
This study presents an innovative, self-synthesized, organo-silane-based adhesion promoter designed to form strong chemical bonds between dissimilar materials such as various dielectric laminates and Cu surfaces (including electrolytically plated Cu). Unlike traditional roughening-based systems, our non-etch solution enables a streamlined two-step process that simplifies manufacturing, reduces costs, and maintains the high bond strength required for next-generation packaging, eliminating the need for aggressive copper etching, our non-etch solution allows for the creation of narrower lines and spaces, which are essential for advanced IC substrate designs.
The system also demonstrates excellent chemical resistance to desmear process, which is necessary to clean blind microvias (BMVs) after laser drilling and prepare them for subsequent Cu filling. Smooth Cu surfaces typically struggle in these harsh conditions, but post-desmear testing of structured designs confirmed the integrity of the sidewalls and minimal wedge formation at the BMV interfaces. Roughness measurements show that our process does not alter the original surface topography. Extended IR Reflow and high-temperature accelerated stress testing (HAST) provide further validation of the durability of the interface. The effectiveness of the promoter in maintaining strong Cu-dielectric bonding under harsh stress conditions is demonstrated by FESEM and FIB analysis.
As a global leader in laser, desmear chemistry and surface treatment, our understanding of interfacial processes extends beyond adhesion alone. This allows us to support customers with fully integrated bonding solutions, combining advanced materials, process integration and application expertise to meet the evolving demands of IC substrate manufacturing.

 

Bio:
Kuan-Cheng Liu is presently Engineer of material technology department of R&D at Siliconware Precision Industries Co., Ltd. (SPIL) Over 1 years of job experience in semiconductor industry (focus on assembly field) and he is in charge of new advanced material development and management in SPIL currently. He has authored/co-authored 1 papers and 2 patents in the advanced packaging field.

Abstract:
In recent years, there has been a shift towards high-density layouts and multi-chip integration in semiconductor packaging technology, resulting in significant challenges regarding package reliability and process efficiency. Against this backdrop, Ball Grid Array (BGA) packages are widely used in high-end computing and communication applications thanks to their high pin count and excellent electrical and thermal performance. However, foreign particulate deposits appearing on the surface of solder balls after reflow can adversely affect the mechanical strength and electromagnetic behaviour of solder joints.
This study involved conducting a surface analysis of soldered balls using scanning electron microscopy (SEM) and energy-dispersive X-ray spectroscopy (EDS). The results revealed that the main component of these particulates is copper. A systematic comparison of different solder alloys and substrate surface finishes (Cu-OSP and Ni/Au) confirmed that copper particle precipitation occurs exclusively when substrates with a Cu-OSP finish are used. Further experimental analysis showed that during initial reflow, flux chemically activates and dissolves copper atoms from the Cu-OSP substrate. These copper atoms are then transported into the molten solder, where they become supersaturated and subsequently precipitate onto the solder ball surface during cooling. Increasing the number of reflow cycles facilitates the re-dissolution of these particles back into the solder. Conversely, reducing the flux acid value and application volume effectively suppresses their precipitation.
This work clearly identifies the Cu-OSP pad as the origin of the copper particles and explains how they are formed via flux-assisted dissolution and precipitation during reflow. These insights enable targeted process optimisation, such as adjusting the flux chemistry and thermal processes, to effectively eliminate copper precipitation. Implementing these measures can improve solder joint quality in BGA packages, thereby supporting the development of stable, high-performance packaging solutions for advanced electronic applications.

 

Bio:
Garian Lim is the Strategic Business Development Manager for Semiconductors at DELO Industrial Adhesives Singapore. With over 20 years of experience in the semiconductor industry, he has held various roles in product development, research and development, sales, and process integration. Before joining DELO, he held position in companies such as Amkor, Statschippac and MacdermidAlpha. Garian holds an B.Eng & M.Eng in Mechanical Engineering from Nanyang Technological University Singapore.

Abstract:
The advent of 5G and artificial intelligence (AI) has driven explosive growth in high-speed data communications, spurring the development of new packaging technologies such as 2.5D/3D advanced packaging for AI applications. Among these silicon photonics packaging is emerging as a promising technology.

Despite significant advancements in electronics packaging, the packaging of photonic integrated circuits (PICs) still faces substantial challenges in achieving high performance and reliability. The silicon photonic packaging process involves numerous technical hurdles, such as the necessity for highly precise and rapid active alignment for optical coupling, reflow and environmental reliability, and managing thermal performance effectively.

This paper provides a comprehensive overview of the key bonding tasks within a photonic package and explores the specific adhesive requirements. In this context the paper focuses on the optical and mechanical properties of adhesives and its capacity to maintain performance under diverse operational conditions with experimental data.

Furthermore, the paper introduces a novel wafer-level photonic packaging approach that preserves optical properties through wafer-level processing steps such as sawing and grinding with experimental data demonstrating its effectiveness.

 

Bio:
Dr. Yu received his Ph.D. in Chemical Engineering from Tsinghua University in 2002. He began his career at the Industrial Technology Research Institute (ITRI), working as a researcher in the Chemical Engineering Division from 2003 to 2007. He then joined Taiwan Semiconductor Manufacturing Company (TSMC), where he contributed to the development of advanced manufacturing processes and technologies. In 2015, Dr. Yu returned to ITRI and is currently with the Electronics and Optoelectronics Research Laboratories. His current research focuses on advanced packaging processes, where he continues to drive innovation and contribute to the semiconductor industry.

Abstract:
With the rapid development of AI technology, AI chips have become a cornerstone of high-end technological applications. A wide range of related products are actively exploring ways to integrate AI capabilities. A hallmark of innovative products and startups is their demand for diverse, small-batch manufacturing. To support the semiconductor industry in tapping into this highly dynamic and innovative market, it is essential to develop new small-batch production models. Our goal is to provide a shuttle service through an innovative platform that significantly reduces the cost and time required to develop new products via shared services. This service model enables startups and emerging products to experiment and iterate at lower costs and higher speeds, helping them reach the market faster and stand out in a competitive environment.
In this article, we present a shuttle service that effectively integrates various applications and structures through wafer layout design, enabling RDL (Redistribution Layer) process fabrication using a mask-sharing approach, as shown in Figure 1. Different applications may have significantly different copper densities. To address this, we further optimized the layout design and adjusted the process conditions, making it feasible to integrate applications with varying copper densities while maintaining excellent process uniformity. We fabricated a structure consisting of six copper metal layers and five corresponding passivation layers using polyimide (PI). Among these, four intermediate metal layers are used for RDL wiring (RDL = 4). From a process perspective, we employed a CTE (Coefficient of Thermal Expansion) compensation mechanism to reduce warpage and integrated low-stress, low-warping process technologies to complete the RDL fabrication. Further warpage reduction was achieved by thinning the PI layers and optimizing layout uniformity. Additionally, a comb structure test pattern was implemented in each metal layer to monitor leakage current, achieving picoampere (pA)-level sensitivity. After the RDL process, electrical testing of all circuits was conducted, resulting in a yield of over 90%. Furthermore, we demonstrate the capability to fabricate fine-pitch multilayer RDL stacks, featuring 2 μm/2 μm line/space and 8 μm via openings with fully copper-filled structures.

 

Bio:
Takanori Fukushima is a doctoral student at the Department of Science and Technology at Gunma University, Japan (2024⁓). His current research focuses on the influence of organic compounds on the sintering phenomenon of silver micro-fillers in resin-bonded conductive adhesives. In 2024, he received the JIEP Poster Award at the International Conference on Electronics Packaging (ICEP).

Abstract:
Sintering-type bonding materials have required improved connection reliability, such as mitigating thermal stress generated in the bonding area due to temperature change as the device operating temperature increases to realize higher device performance. We have been conducting fundamental research on sintering-type bonding, focusing on “low-temperature sintering of metal micro-fillers in resin-bonded conductive adhesives,” which can be used in large-area bonding applications such as module attachment.
In this study, we conducted fundamental research on applying the flexible epoxy resin as a conductive adhesive binder, expecting to enhance the stress-easing properties of the cured adhesive layer. We investigated the effects of application of the main component of flexible epoxy resin, the addition of reactive diluents, and the types of diluents on the low-temperature sintering behavior of silver micro-flakes and adhesive bonding properties.
The binder for the ECAs was prepared by using one of two types of two functional glycidyl ether epoxy resins, bisphenol A diglycidyl ether (BPA) and flexible-epoxy-resin as the primary component, with imidazole curing catalyst as hardener. Furthermore, various reactive diluents, including phenyl glycidyl ether (PGE), were added to the adhesive in specified amounts.
It has been found that applying flexible epoxy reduces electrical resistivity. In the flexible-epoxy resin based sample with 40 wt% PGE, the electrical resistivity of 10-6 ·cm, which was obtained by curing at 250 °C or higher in the BPA-resin based sample, could be obtained after curing at 190 °C.
Next, evolutions in the condition of cross-sectional microstructure cured at 190°C and 250 °C were evaluated. For both primary component samples, sintering between micro-flakes in the adhesive progressed depending on the curing temperature. Comparison of the applied primary components showed that sintering progressed more at both curing temperatures in the flexible epoxy resin-based samples than in the BPA resin samples. The results indicated that the application of flexible epoxy resin contributes to accelerated sintering.
The species of reactive diluent is also expected to influence resulting properties. Comparing the electrical resistivity of samples containing various reactive diluents with various structures, it was found that the effects of the added diluents varied. In samples containing the reactive diluent, which has a benzene ring and a carboxylic acid ester (EPGD) , it was found that electrical resistivity decreased more than in samples containing PGE.
Next, the electrical connection properties of the adhesion interface with the Cu electrode were evaluated by measuring the interfacial electrical resistivity. Using the flexible epoxy resin as the primary component was also found to improve the conductivity of the adhesion interface.
Furthermore, the viscoelastic properties of the freestanding samples of the adhesives to which each of the two main components was added were measured by dynamic mechanical analysis. Flexible epoxy as the primary component was more flexible.
It showed that the flexible epoxy resin binder composition designed to utilize chemical interactions between Ag fillers can be used to obtain a conductive adhesive that can be cured at low temperatures, is flexible, and has excellent bonding properties.