Sessions Index

Bio:

Jimmy Hsu serves as a Principal Engineer within Intel's Data Center and AI Group, where he leads the development of interconnect solutions for high-speed interfaces. He earned both his Bachelor of Science and Master of Science degrees in Control Engineering from National Chiao Tung University, in 1998 and 2000, respectively.
His research primarily focuses on high-speed design, with particular emphasis on power integrity, signal integrity, and electromagnetic interference (EMI). Throughout his career, he has contributed to 80 international publications and has been granted 16 US patents, underscoring his significant contributions to the field of high-speed interface technology.

Abstract:

• Evolution of High-Speed Technologies in Data Center and AI Applications

• Evolution of High-Speed Technologies in Data Center and AI Applications

• Challenges in High-Speed Design

• Advancements in PCB Electrical Characterization

• Enabling the PCB Ecosystem

• Summary

 

Bio:
1. Major in Chemical Engineering & Materials Science at Yuan Ze University. 2. Research expertise: Electrochemistry, Thermal Module Applications, Finite Element Analysis.

Abstract:
The continuous miniaturization of electronic devices along with the rapid increase in current density has led to a significant rise in power consumption and an urgent demand for thermal modules in recent years. Copper (Cu) is widely used as a conductive and heat-dissipating material in many PCBs and IC devices due to its low resistivity, high thermal conductivity, superior electromigration resistance, and excellent mechanical properties. Recently, a “bar via” structure, i.e., an array of slender Cu strips arranged in a trench-type layout, has gained a great deal of attention in the PCB’s thermal module design because it greatly raises the efficiency of thermal dissipation, while preserving process and routing flexibility. The surface flatness of electroplated Cu above the bar via structure is one of the critical factors, dominating the thermal dissipation efficiency of thermal module and affecting the reliability of PCB build-up process. The morphological modification of Cu electrodeposition in the bar via structure through electroplating parameters (e.g., organic additives or flow field) was therefore conducted in the present study. Our established electrochemical simulation model can well characterize the Cu electrodeposition behavior in the bar via structure and electroplating parameters (organic additives or flow field) may play critical roles in the Cu electrodeposition morphology in bar via structures. The electrochemical simulation techniques established in this study would facilitate the development of thermal module for high-power RF components.

 

Bio:
more than five years of signal integrity

Abstract:
As data rates for PCIe signals continue to rise and modulation shifts from Non-Return-to-Zero (NRZ) to Pulse Amplitude Modulation with 4 Levels(PAM4), DDR signaling is also advancing from 8800 MT/s to 12800 MT/s. These transitions significantly elevate the importance of channel quality. To meet these demands, more stringent electrical requirements have been proposed, and close collaboration with PCB vendors is underway to validate and manufacturing process variations. This collaboration ensures consistent and reliable production processes, enabling designers to more easily meet the new electrical specifications and achieve their design goals with high performance and reliability.
A comprehensive analysis will be conducted across multiple PCB vendors using Intel ® Automatic In-Board Characterization. This analysis will validate impedance and loss management across critical interconnect areas such as vias, pin fields, and main routing paths. Additionally, it will detect the impedance variation in transition areas and P/N skew for differential signals, highlighting the impedance mismatches are becoming increasingly critical for next generation data center platform. To support platform design optimization, an electrical design library will be developed serving as a reference for achieving consistent signal integrity and performance across diverse manufacturing processes.

By empowering the PCB ecosystem with not only advanced manufacturing capabilities and quality standards but also state-of-the-art measurement technologies, superior design outcomes have been achieved for platform designers. The next generation PCB design requirements emphasize high-speed application needs, particularly via and pin field impedance control, in addition to conventional open-field routing. This initiative supports ecosystem enablement by showcasing PCB vendor capabilities, promoting consistent design quality, and streamlining manufacturing management across diverse suppliers. Ultimately, this approach helps platform designers meet evolving electrical requirements and deliver high-performance, reliable products.

 

Bio:
More than 12 years of working experience in signal integrity

Abstract:
As high-speed signals evolve, PCI Express (PCIe) transitions from Gen5 to Gen6, and DDR5 RDIMM (Registered Dual In-line Memory Module) and MRDIMM (Multiplexed Rank Dual In-Line Memory Module) also increase to 8800 MT/s and 12800 MT/s, respectively. As a result, channel integrity has become more critical than ever, prompting an increase in the number of package pins in Intel’s upcoming platform to improve the SNR (Signal-to-Noise Ratio). This change has made the dual processor (a.k.a. 2 sockets, 2S) 16 channels (CH) configuration incompatible with standard 19-inch rack dimensions, presenting a significant integration challenge. Intel has launched a strategic initiative to support 16 channels within a 19-inch rack on its upcoming Server platform. This effort is intended to meet customer demands for high-density DDR deployment in a standard 2S 19-inch rack configuration.
This approach to addressing the challenge involves a carefully crafted proposal to reduce the DIMM pitch and processor keep-out zone. It is supported by a comprehensive risk assessment that covers the entire channel simulation, ensuring all potential issues are thoroughly evaluated and mitigated. The assessment includes crosstalk comparison between the standard and narrow DIMM pitches configurations, thereby ensuring the overall signal integrity (SI) quality of the channel design.
Two notable design enhancements are the integration of VIPPO (Via-In-Pad Plated Over) technology in the DDR connector area and the reduction of the DIMM-to-DIMM distance (also known as narrow DIMM pitch), as illustrated in Figure 1. VIPPO provides additional routing space, which is essential for maintaining signal integrity as DDR speeds increase, particularly for MRDIMM. By allowing vias to be placed directly inside the pad, VIPPO shortens path and improves signal integrity. This design not only enhances electrical performance but also optimizes the physical layout, enabling more channels to fit within a 19-inch chassis. The adoption of VIPPO underscores Intel’s commitment to pioneering advanced solutions that address complex technical challenges while meeting the evolving needs of its customers.
SI comparisons between non-VIPPO and VIPPO are shown, demonstrating that VIPPO not only preserves routing space but also significantly improves signal margin in the DDR channel, ensuring robust performance in high-speed applications. The comparison highlights the advantages of VIPPO, including reduced crosstalk, improved signal integrity, and elegant PCB routing, making it a key strategy for delivering high-performance computing solutions in next-generation 19-inch rack designs.

 

Bio:
Zi-An Huang received the B.S. degree from the Department of Mechanical and Computer-Aided Engineering, National Formosa University, Huwei, Taiwan, in 2018, and the M.S. degree in advanced intelligent manufacture for electric vehicle from National Tsing Hua University, Hsinchu, Taiwan, in 2024,He is currently a Engineer with Structural Design Section, Acbel Polytech Inc., His research interests include power supply structure design , electronic package designs and semiconductor-related manufacturing processes.

Abstract:
The reliability of the electronic is the important issue for the product. In this study, based on to the recent huge demand in artificial intelligence and big data applications, more technical researches are focused on how to improve and enhance the efficacy of data center design. Furthermore, the designs of IT equipment and power supplies system are influenced the specification of data center in the international tier systems, depended on maximum permitted downtime and backup power supply. In the study, mechanical estimation is utilized to assist the engineering development in MLCC of PCB floorplan design. On the other hand, enhancing the products life and reliability of power supply are critical role. In the hardware of power supply, one persistent headache is the mismatch in thermal coefficient expansion between different materials, especially during high temperature application environment especially aging conditions. Moreover, the plastic deformation associated with creep physical behavior progressively is accumulated, eventually causing mechanical issues like solder crack or delamination during the operation of power supply. From previous references, these mechanical failure behaviors influence electrical failures or even breakdowns. In addition, our experimental results show high reproducibility with physical behaviors from previous literatures.
Research indicates that the placement of components on the board has a measurable impact on their reliability and structural strength. these factors influence the lifetime of power supplies. However, tweaking the layout for reliability isn’t not without cost, these changes may sometimes reduce performance. Consequently, there is few perfect solutions for satisfying physical demand. It makes sense to consider multiple layout strategies MLCC of PCB floorplan design that balance lifetime with other design priorities. Product lifetime is an important parameter in reliability research, completion of validation experiments will enable effective control of product lifespan. In this study, we are aims to develop a practical framework that integrates Coffin Manson lifetime modeling via nonlinear finite element analysis (FEA) and multilayer perceptron of neural networks, all aiming to achieve a more accurate depiction of reliability and to identify novel approaches for prolonging product life. Furthermore, solder materials, integrated with Anand model, are considered in this study. After validated FEA via experiments, the difference is lower than 10%. The database from mechanical simulation accounts for 250 sets. 80% database is used for the training in Neural Networks. In addition, others are utilized to process the testing. This strategy enables to provide multiple robust designs for selection of design engineering between mechanical and electrical domains in MLCC of PCB floorplan design.

 

Bio:
Ph.D student from NCKU (Program on Semiconductor Packaging and Testing, Academy of Innovative Semiconductor and Sustainable Manufacturing)

Abstract:
Solid liquid interdiffusion (SLID) which was also well-known as
transient liquid phase (TLP) bonding derives from 1970s for
connecting high melting point Ni based alloy at relative low bonding
temperatures to reduce the cost of heating process. TLP process
includes interlayer melting, dissolution, isothermal solidification, and
homogenization. After the joint bonded, the interlayer will transform
into high melting point intermetallic compounds (IMCs). Advanced
packaging requires high stability in extreme operating conditions of
high temperatures, however due to the shrinkage of bonding size and
solder joints were fully transformed into IMCs, the traditional
soldering process poor reliability and brittle in thermal cycling tests.
Tin (Sn), Indium (In) and Gallium (Ga) are commonly selected as
interlayer materials because of their low melting point. Notably, Ga
exhibits a wide solubility in copper (Cu), which makes it highly
promising to form solid solution joint for Cu-to-Cu interconnection.
In our previous work, Cu/Ni/Ga/Ni/Cu sandwich couple will
transform into Cu/fcc-(Ni,Cu,Ga)/Cu structure and show great
thermal reliability in high temperature storage. In order to achieve Ga
solid solution TLP bonding, precise transfer for liquid Ga is required,
but it is very difficult because of its high surface tension. CuGa2,
Cu9Ga4, Ni3Ga7 and Ni2Ga3 these IMCs are commonly found in Cu
Ga or Cu-Ni-Ga bonding joints if Ga transfer isn’t properly controlled.
In this study we proposed an electroplating Ga method for Cu
substrate and Ni UBM to achieve precise transfer for Ga. The
interfacial reaction during electroplating will be disclosed, and the
effect of Ni UBM thickness on composition of electroplated thin films
will be studied. Surface and cross-sectional morphology will be
demonstrated by the field-emission SEM. Phase transformation at
different temperatures during heating process will be determined by
XRD. To achieve Ga TLP bonding for Cu-to-Cu interconnection, we
have to make sure that the interlayer can transform into Ga liquid
phase and react with substrates. Ga particles synthesis and Ga thin
film deposition technology of Ga and Ga-based alloy have been
widely studied for 3D IC packaging or TIM material owing to its low
melting point and non-toxic properties. Although electroplating Ga
technology still facing low current efficiency issue and coalescence
of the plated thin film which attributes to the poor wettability on
substrate, electrodeposition makes Ga TLP bonding a better chance to
fabricate high reliability joints. The solid solution TLP bonding was
considered to be one of the most potential methods in next generation
packaging technology for the power modules.

 

Bio:
Master’s student in Professor Jenn-Ming Song’s Laboratory, Department of Materials Science and Engineering, National Chung Hsing University, focusing on direct bonding research for advanced semiconductor packaging.

Abstract:
Solder mask, also called solder resist, refers to a thermally stable and thin polymeric coating applied to the non-soldered areas of printed circuit boards (PCBs) and component substrates, such as those used in flip-chip packaging and wire bonding. Additionally, solder mask plays a crucial role in advanced packaging due to their good insulation properties, which protect copper circuits from oxidation and prevent outside moisture from penetrating and corroding the circuitry. Once cured, solder mask doesn’t release emitted gases or moisture, contributing to its low volumetric shrinkage—an essential feature for high-precision applications. Considering the bond between polyimide (PI) and solder mask is crucial for the reliability of flexible printed circuits and other electronic assemblies, direct bonding between solder mask and PI was developed in this studied. Surface treatments were performed using three different irradiation wavelengths: vacuum ultraviolet (VUV, 172 nm), UV-C (254 nm)/VUV (185 nm), and UV-C (220 nm), followed by thermal compression bonding (TCB). Experimental results show that a greater amount of surface functional groups did not consistently lead to enhanced interfacial bonding strength between these two polymer materials. For further understanding, nanoindentation techniques were conducted to characterize the mechanical properties of the treated surfaces and the discussion was made with the chemical characteristics.