Sessions Index

Bio:

2021 Completed a master's degree in engineering at Hokkaido University
2021/4~ Work at Mitsubishi Materials Corporation.
Research Electroplating and Pacaging Process

Abstract:

・Fine pitch interconnects
・Direct Bonding
・Porous Structures

 

Bio:

In March 2022, I graduated from Tohoku University with a Master's degree in Environmental Science.
In April 2022, I joined Kao Corporation and have been responsible for my current duties since then.

Abstract:

We present our work on copper particles that exhibit high dispersibility and can be sintered at low temperatures. These particles can be stably dispersed at high concentrations in a wide range of solvents. When used as copper bonding materials for power semiconductor
applications, the resulting bonded structures demonstrate excellent thermal stability.
We are currently evaluating their performance as bonding materials for power semiconductors.
We also plan to investigate their potential as conductive paste used in semiconductor packaging and multilayer ceramic capacitors (MLCCs).

 

Bio:

Kejun Wu is a Research and Development Engineer at Ushio Inc., specializing in the applied development of 172 nm wavelength ultraviolet light generated by excimer lamp. He graduated from the Graduate School of Tokushima University with a degree in Optical Systems. During his first three years at Ushio, he focused on the surface modification of fluororesins and the formation of copper plating using excimer lamps. Currently, in his fourth year, he is engaged in developing activation processes for hybrid bonding through excimer lamp treatment. Originally from Taiwan, Wu is now based in Japan and has presented his research at various conferences, including The Surface Finishing Society of Japan, the Microelectronics Symposium 2024, and The Japan Institute of Electronics Packaging.

Abstract:

Three-dimensional integration technology has emerged as a promising solution to overcome scaling challenges in advanced semiconductor device technologies. This approach involves vertically stacking multiple chips, which shortens interconnect lengths and enable higher integration density. A crucial method within 3D integration is hybrid bonding (HB), which facilitates fine-pitch wiring connections necessary for advanced semiconductor devices.
In the HB process, it is essential to remove organic contaminants from the Cu/SiO2 surface and modify the SiO2 surface with functional groups such as OH species, while preventing surface roughening and avoiding oxidation of the Cu electrodes. Plasma treatment effectively achieves such surface cleaning and introduction of OH, but it induces surface roughening due to high-energy particles.
As an alternative process, vacuum ultraviolet (VUV) cleaning has been proposed. Conventional VUV cleaning process under water vapor environments dissociates O2 and H2O to generate reactive species that eliminate organic contaminants but oxidize metal electrodes. To solve this problem, VUV treatment under an N2/H2 atmosphere with added H2O was reported, which effectively removed organic contaminants and reduced copper oxide. Here, we investigated the effects of VUV light irradiation under an N2/H2 + H2O atmosphere on the surface activation and bonding strength of Cu/SiO2 samples that simulate actual semiconductor materials for hybrid bonding.
VUV light with a central wavelength of 172 nm, emitted from a xenon excimer lamp (STN3-317, Ushio Inc.), was irradiated onto SiO2 substrates with copper patterns (Cu/SiO2) under a gas atmosphere that was prepared by bubbling a mixed gas of N2 and 4 % H2 through liquid water (N2/H2+H2O atmosphere). The surface chemical states were analyzed by X-ray photoelectron spectroscopy (ULVAC-PHI, PHI Quantera II). The surface roughness was measured by atomic force microscopy (SPM-9700HT, Shimadzu).
The XPS spectra after VUV treatment for 45 s under the N2/H2 + H2O atmosphere significantly decreased surface organic contaminants and effectively reduced copper oxide. The XPS analysis confirmed the presence of OH species on the surface after treatment. The surface roughness showed no appreciable change on the Cu electrode and a reduced arithmetic mean roughness (Ra) of SiO2 surface after the treatment. Finally, bonding strength was evaluated using die shear testing. The VUV treated Cu/SiO2 samples were pre-bonded at room temperature, achieving a maximum shear bonding strength of 10.68 MPa. After heating to promote the expansion and diffusion bonding of the Cu electrodes, the bonding strength increased to a maximum of 17.71 MPa.
These results demonstrate that VUV treatment under N2/H2 + H2O atmosphere is a promising activation method for hybrid bonding, offering effective contaminant removal, surface activation, and enhanced bonding strength without surface damage within a short processing time.

 

Bio:

Takashi Tasaki graduated from the Department of Materials Science and Engineering at the Graduate School of Engineering at Kyushu University in 2003, after which he joined Arakawa Chemical Industries, Ltd. Since then, he has specialised in developing and marketing electronic insulation materials.

Abstract:

Digital transformation in various industries has led to an increased demand for processing large amounts of data, resulting in a demand for higher performance in electronic devices. To meet these requirements, the semiconductor industry is adopting heterogeneous chiplet integration technology. In this context, redistribution layers (RDLs) are critical components for heterogeneous integration. In the future, higher performance will require insulating materials with low dielectric properties for high-speed transmission and good flexibility for warpage control of the heterogeneously integrated package. In response to these technical trends, we have developed novel polyimide compositions for RDLs. Firstly, our polyimide compositions have a low Dk/Df of 2.4/0.002 at millimetre frequency. Secondly, they have good flexibility, i.e. a low modulus of approximately 1 GPa and a high elongation of around 100%. These properties are effective for warpage control by stress relaxation. Finally, the layers of our polyimide compositions are suitable for a semi-additive process, enabling us to produce fine lines and spaces of 2/2 µm on our polyimide layers. We can also create vias through solvent development following i-line exposure. Therefore, we conclude that our polyimide compositions are suitable for use as dielectric materials in RDLs for future HPC applications.

 

Bio:

Mr. Reito Kobayashi is the part of JCU Corporation which produces equipment and chemicals for plating industry both decorative and
electronics. Since he joined electronics technology development, he has been developing the additives for copper plating process.

Abstract:

As limitations of the Si interposer due to insertion loss at high frequencies are expected in the future, new structures, such as glass interposers and fan-out interposers, are being considered as substitutes. These new structures require brand new chemicals to achieve large-scale filling, void-free deposition, and high uniformity in TGV, TSV, and RDL, respectively. To meet future demand, we have developed surface treatment chemicals for each application.

 

Bio:

Masafumi Wakai received his Bachelor's degree from the Department of Electrical and Electronic Engineering from University of Shinshu, Japan, in 2006. Since then, he has been working at the research institute of ULVAC, Inc., where he has contributed to the development of CVD for electrical devices and flat panel display. After that he developed sputtering targets for oxide semiconductors and alloys. Since 2023, he has been responsible for the development of sputtering technology for GaN devices and panel level packaging at ULVAC. Outside of work, he enjoys soft tennis and scuba diving.

Abstract:

The next era of AI-driven information and communications technology (ICT) systems will be powered by an infrastructure that integrates Cloud Computing, Fog and Edge Computing, and Massive IoT. New semiconductor devices are necessary for artificial intelligence (AI) that require real-time or low-latency performance (less than 1ms), as well as low power consumption. High-density packaging technologies, including 3D chiplet integration with wafer-level packaging (WLP) and panel-level packaging (PLP), are essential to meet the manufacturing requirements of these high-performance semiconductor devices. ULVAC has been continuously developing manufacturing solutions to achieve heterogeneous integration through substrate packaging, 2.5D interposers, and 3D-IC technologies, including through-glass vias (TGV), through-silicon vias (TSV) and hybrid bonding. In this presentation, ULVAC will outline our efforts in heterogeneous chiplet integration, which involve PVD (Physical Vapor Deposition) sputtering techniques and plasma etching/ashing to achieve high-density interconnections.